BSIM4 Gate Leakage Model Including Source-Drain Partition

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4. Introduction As the gate length of MOSFETs is reduced to the sub100nm regime, gate oxide thickness of sub-20Å prevails in CMOS processes [1]. Besides the benefits of high drive current and low DIBL effect, such thin oxide yields significant gate leakage current by various direct tunneling mechanisms [2], with undesirable effects on standby current and memory operation [3]. Comparing to the compact leakage current models for MOS capacitors [4,5], less research has been conducted on the compact MOSFET models. C.-H. Choi [6] proposed a gate leakage model for MOSFET but the model is not accurate under low bias condition (in direct-tunneling regime) and the current partition scheme is unphysical. In this work, a physical gate leakage model for MOSFET is developed and implemented in BSIM4. Firstly, we propose an accurate gate leakage model for the MOS capacitor. Then a physical source-drain current partition model is introduced. The model is verified with experimental data and 2D simulation. MOS Capacitor Leakage Model Lee and Hu proposed an accurate dielectric leakage model for MOS capacitors [5]. A simplified version of this model with little compromises on accuracy is the basis of the MOSFET gate leakage model. There are three major leakage mechanisms for a MOS structure, namely, electron conduction-band tunneling (ECB), electron valence-band tunneling (EVB), and hole valence-band tunneling (HVB), as illustrated in Fig. 1. Each mechanism is dominant or important in different regions of operation for PMOS and NMOS as shown in Table 1. For each JECB JEVB φECB,SiO2 = 3.1 eV